Redundant clock transistion tolerant latch circuit

ABSTRACT

Embodiments of a latch circuit and a method of operating a latch circuit are described. In one embodiment, a latch circuit includes an input terminal configured to receive an input data signal, a switching unit configured to control application of the input data signal, a first inverter circuit connected to the switching unit, where the first inverter circuit includes a first cross-coupled pair of inverters, and a second inverter circuit connected to the first inverter circuit through the switching unit. The second inverter circuit includes a second cross-coupled pair of inverters and two transistor devices. Each inverter of the second cross-coupled pair of inverters is connected to a voltage rail through a corresponding transistor device. Each of the two transistor devices is connected to a node that is between the switching unit and the first inverter circuit or the second inverter circuit. Other embodiments are also described.

This application claims priority from European Patent Application No.EP13191288, filed Nov. 1, 2013, which is incorporated herein byreference in its entirety.

Embodiments of the invention relate generally to electronic hardware andmethods for operating electronic hardware, and, more particularly, tolatch circuits and methods for operating latch circuits.

The power consumption of an electronic circuit is an importantperformance metric. For example, for low power embedded devices such asmicrocontrollers and smartcards, reducing the power consumption isimportant to the performance of the device. Dynamic power consumptioncaused by redundant clock transitions of digital devices can account fora significant portion of the overall power consumption of digitaldevices. Specifically, charging and discharging of internal nodes of alatch circuit in which the input data of the latch circuit is in thesame state for consecutive clock cycles result in unnecessary powerconsumption. For example, dynamic power consumption caused by redundantclock transitions can account for around 50% of the power consumption ofa latch circuit. The reduction in power consumption by redundant clocktransitions can reduce the overall power consumption of a latch circuitand improve the power efficiency of the latch circuit. Therefore, it isdesirable to reduce power consumption caused by redundant clocktransition in a latch circuit.

Embodiments of a latch circuit and a method of operating a latch circuitare described. In one embodiment, a latch circuit includes an inputterminal configured to receive an input data signal, a switching unitconfigured to control application of the input data signal, a firstinverter circuit connected to the switching unit, where the firstinverter circuit includes a first cross-coupled pair of inverters, and asecond inverter circuit connected to the first inverter circuit throughthe switching unit. The second inverter circuit includes a secondcross-coupled pair of inverters and two transistor devices. Eachinverter of the second cross-coupled pair of inverters is connected to avoltage rail through a corresponding transistor device. Each of the twotransistor devices is connected to a node that is between the switchingunit and the first inverter circuit or the second inverter circuit. Thelatch circuit implements data aware power gating to reduce or eliminatedynamic power consumption caused by redundant clock transitions withinthe latch circuit. Other embodiments are also described.

In an embodiment, a latch circuit includes an input terminal configuredto receive an input data signal, a switching unit configured to controlapplication of the input data signal, a first inverter circuit connectedto the switching unit, where the first inverter circuit includes a firstcross-coupled pair of inverters, and a second inverter circuit connectedto the first inverter circuit through the switching unit. The secondinverter circuit includes a second cross-coupled pair of inverters andtwo transistor devices. Each inverter of the second cross-coupled pairof inverters is connected to a voltage rail through a correspondingtransistor device. Each of the two transistor devices is connected to anode that is between the switching unit and the first inverter circuitor the second inverter circuit.

In an embodiment, a latch circuit includes an input terminal configuredto receive an input data signal, a switching unit, a first invertercircuit, and a second inverter circuit. The switching unit includes afirst inverter configured to generate an inverted version of the inputdata signal from the input data signal, a second inverter connected tothe first inverter and configured to generate a non-inverted version ofthe input data signal, a first set of switching transistors of a firstpolarity type, where the first set of switching transistors areconnected to the first and second inverters and a second set ofswitching transistors of a second, opposite, polarity type. The firstinverter circuit is connected to the first and second sets of switchingtransistors and includes a first cross-coupled pair of inverters. Thesecond inverter circuit is connected to the first inverter circuitthrough the second set of switching transistors. The second invertercircuit includes a second cross-coupled pair of inverters and twotransistor devices. Each inverter of the second cross-coupled pair ofinverters is connected to a low voltage rail and to a high voltage railthrough a corresponding transistor device. Gate terminals of the twotransistor devices are cross-connected to drain terminals or sourceterminals of the second set of switching transistors.

In an embodiment, a method for operating a latch circuit involvesreceiving input data at the latch circuit and discharging or charginginput nodes of a cross-coupled pair of inverters of the latch circuit ifthe input data is different for consecutive clock cycles of the latchcircuit.

Other aspects and advantages of embodiments of the present inventionwill become apparent from the following detailed description, taken inconjunction with the accompanying drawings, depicted by way of exampleof the principles of the invention.

FIG. 1 is a schematic block diagram of a latch circuit in accordancewith an embodiment of the invention.

FIG. 2 depicts an embodiment of the latch circuit depicted in FIG. 1.

FIG. 3 depicts another embodiment of the latch circuit depicted in FIG.1.

FIG. 4 depicts another embodiment of the latch circuit depicted in FIG.1.

FIG. 5 shows the latch circuit of FIG. 4 with a low phase of a clocksignal.

FIG. 6 shows the latch circuit of FIG. 4 with a rising edge of the clocksignal.

FIG. 7 shows the latch circuit of FIG. 4 in an active hold state.

FIG. 8 shows the latch circuit of FIG. 3 in a retention state.

FIG. 9 illustrates some examples of signals of the latch circuitsdepicted in FIG. 3 and FIG. 4.

FIG. 10 is a process flow diagram that illustrates a method foroperating a latch circuit in accordance with an embodiment of theinvention.

Throughout the description, similar reference numbers may be used toidentify similar elements.

It will be readily understood that the components of the embodiments asgenerally described herein and illustrated in the appended figures couldbe arranged and designed in a wide variety of different configurations.Thus, the following detailed description of various embodiments, asrepresented in the figures, is not intended to limit the scope of thepresent disclosure, but is merely representative of various embodiments.While the various aspects of the embodiments are presented in drawings,the drawings are not necessarily drawn to scale unless specificallyindicated.

The described embodiments are to be considered in all respects only asillustrative and not restrictive. The scope of the invention is,therefore, indicated by the appended claims rather than by this detaileddescription. All changes which come within the meaning and range ofequivalency of the claims are to be embraced within their scope.

Reference throughout this specification to features, advantages, orsimilar language does not imply that all of the features and advantagesthat may be realized with the present invention should be or are in anysingle embodiment. Rather, language referring to the features andadvantages is understood to mean that a specific feature, advantage, orcharacteristic described in connection with an embodiment is included inat least one embodiment. Thus, discussions of the features andadvantages, and similar language, throughout this specification may, butdo not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics ofthe invention may be combined in any suitable manner in one or moreembodiments. One skilled in the relevant art will recognize, in light ofthe description herein, that the invention can be practiced without oneor more of the specific features or advantages of a particularembodiment. In other instances, additional features and advantages maybe recognized in certain embodiments that may not be present in allembodiments of the invention.

Reference throughout this specification to “one embodiment,” “anembodiment,” or similar language means that a particular feature,structure, or characteristic described in connection with the indicatedembodiment is included in at least one embodiment. Thus, the phrases “inone embodiment,” “in an embodiment,” and similar language throughoutthis specification may, but do not necessarily, all refer to the sameembodiment.

FIG. 1 is a schematic block diagram of a latch circuit 100 in accordancewith an embodiment of the invention. In the embodiment depicted in FIG.1, the latch circuit includes an input terminal 102, a switching unit104, a first inverter circuit 106, a second inverter circuit 108, and anoutput terminal 110. The latch circuit can be used in variousapplications, such as automotive applications, communicationsapplications, industrial applications, medical applications, computerapplications, and/or consumer or appliance applications. The latchcircuit can be implemented in a substrate, such as a semiconductor waferor a printed circuit board (PCB). In an embodiment, the latch circuit isincluded in a low power system-on-chip (SoC). For example, the latchcircuit may be included in a low power cryptographic SoC. Although thelatch circuit is shown in FIG. 1 as including certain components, insome embodiments, the latch circuit includes less or more components toimplement less or more functionalities. For example, the latch circuitmay include a clock source or a voltage source.

The input terminal 102 of the latch circuit 100 is configured to receivean input data signal. The output terminal 110 of the latch circuit isconfigured to output an output data signal in response to the input datasignal.

The switching unit 104 of the latch circuit 100 is configured to controlapplication of the input data signal. In some embodiments, the switchingunit controls application of the input data signal to the first invertercircuit and to the second inverter circuit. The switching unit mayinclude a first set of switches that includes transistors of a firstpolarity type and a second set of switches that includes transistors ofa second, opposite, polarity type.

The first inverter circuit 106 of the latch circuit 100 is connected tothe switching unit 104 and includes a first cross-coupled pair 112 ofinverters 114, 116. A cross-coupled pair of inverters is also referredto as a cross-coupled inverter pair (CCIP). The second inverter circuit108 of the latch circuit is connected to the first inverter circuitthrough the switching unit. The second inverter circuit includes asecond cross-coupled pair 122 of inverters 124, 126, and at least twotransistor devices 128, 130. In some embodiments, each inverter of thesecond cross-coupled pair of inverters is connected to a voltage rail132 through a corresponding transistor device 128 or 130. The voltagerail may have a positive voltage. Alternatively, the voltage rail may beconnected to the ground. In these embodiments, each of the twotransistor devices is connected to a node that is between the switchingunit and the first inverter circuit or the second inverter circuit. Insome embodiments, the first inverter circuit 106 is a master invertercircuit and the second inverter circuit 108 is a slave inverter circuit.In these embodiments, a change in state of the first inverter circuitcauses a change in state of the second inverter circuit.

Latch circuits, such as a Master-Slave D-type flip-flop, a “clock ondemand” flip-flop, and a master slave flip-flop, as described inEuropean Patent Application No. EP13191288, use clock gating to turn offthe clocking of the portion of the latch circuit that is not in use.However, clock gating can be ineffective for situations in which thedata sampled by the clocked element is identical for two consecutiveclock cycles. The redundant switching of the internal nodes of a latchcircuit caused by the clock signal, when the input data at the inputterminal 102 is in the same state for consecutive clock cycles, maycause an unnecessary increase in the power consumption (e.g., unnecessary charging and discharging of internal node parasiticcapacitances). In the embodiment depicted in FIG. 1, input data awarepower gating can be implemented by connecting each of the two transistordevices 128, 130 to a node that is between the switching unit 104 andthe first inverter circuit 112 or the second inverter circuit 122.Compared to other retention latch circuits, the latch circuit 100depicted in FIG. 1 exhibits reduced power consumption, eliminates extracontrol signals, and reduces area overhead due to redundant switching byinput data aware power gating. In addition, compared to other latchcircuits, the latch circuit depicted in FIG. 1 does not require aninternal clock-buffer. Further, compared to other latch circuits, thelatch circuit depicted in FIG. 1 can use single phase clocking, andtherefore does not need internal clock signal inversion. The latchcircuit depicted in FIG. 1 can be implemented with low power, with nodynamic power consumption for redundant transitions when the input datasignal and the output data signal are the same.

In some embodiments, gate terminals of the two transistor devices 128,130 of the second inverter circuit 108 are cross-connected to nodesbetween the switching unit 104 and the second cross-coupled pair ofinverters 122. FIG. 2 depicts an embodiment of the latch circuit 100depicted in FIG. 1 in which gate terminals, “G,” of two transistordevices 260, 262 of a slave inverter circuit 208 are cross-connected tonodes 282, 272 between a switching unit 204 and a cross-coupled inverterpair (CCIP) 222 (referred to as the slave CCIP) of the slave invertercircuit. In the embodiment depicted in FIG. 2, a latch circuit 200includes an input terminal, “DIN,” the switching unit 204, a masterinverter circuit 206 having a cross-coupled inverter pair (CCIP) 222(referred to as the master CCIP), the slave inverter circuit 208 havingthe slave CCIP 222, an inverter 227, and an output terminal, “DOUT.” Achange in state of the master inverter circuit causes a change in stateof the slave inverter circuit. In the embodiment depicted in FIG. 2,input data aware power gating is implemented for the slave invertercircuit 208.

The latch circuit 200 depicted in FIG. 2 is one possible embodiment ofthe latch circuit 100 depicted in FIG. 1. However, the latch circuit 100depicted in FIG. 1 is not limited to the embodiment shown in FIG. 2.

In an embodiment, the input terminal, “DIN,” is configured to receive aninput data signal. The output terminal, “DOUT,” is configured to outputan output data signal in response to the input data signal.

The switching unit 204, which includes an inverter circuit 240 and aswitching module 242, is configured to control the application of theinput data signal received from the input terminal, “DIN,” to inverters214, 216 of the master CCIP 212 and to inverters 224, 226 of the slaveCCIP 222. The inverter circuit 240 is configured to generate an invertedversion, “DBN,” of the input data signal and a non-inverted version,“DB,” of the input data signal. In the embodiment depicted in FIG. 2,the inverter circuit 240 includes inverters 244, 246. The inverter 244is connected to the input terminal, “DIN,” and is configured to generatethe inverted version, “DBN,” of the input data signal. The inverter 246is configured to generate the non-inverted version, “DB,” of the inputdata signal. The switching module 242 is configured to switch either theinverted version, “DBN,” or the non-inverted version, “DB,” of the inputdata signal to an input terminal of the master CCIP 212 or the slaveCCIP 222 and to switch the other one of the inverted and non-invertedversions of the input data signal to an output terminal of the masterCCIP 212 or the slave CCIP 222. In the embodiment depicted in FIG. 2,the switching module includes a first set of switches that areimplemented as PMOS transistors 250, 252, and a second set of switchesthat are implemented as NMOS transistors 256, 258. The transistor 250 isconfigured to switch the inverted version, “DBN,” of the input datasignal to an input terminal 290 of the master CCIP 212. The transistor252 is configured to switch the non-inverted version, “DB,” of the inputdata signal to an output terminal 292 of the master CCIP 212. Thetransistor 256 is configured to switch the inverted version, “DBN,” ofthe input data signal to an input terminal 282 of the slave CCIP 222.The transistor 258 is configured to switch the non-inverted version,“DB,” of the input data signal to an output terminal 272 of the slaveCCIP 222.

The master inverter circuit 206 includes the master CCIP 212, whichincludes inverters 214, 216. The inverters 214, 216 are connectedback-to-back. As shown in FIG. 2, the output terminal of the inverter214 is connected to the input terminal of the inverter 216, while theoutput terminal of the inverter 216 is connected to the input terminalof the inverter 214.

The slave inverter circuit 208 is connected to the master invertercircuit 206 through the switching unit 204. In the embodiment depictedin FIG. 2, the slave inverter circuit includes the slave CCIP 222 withthe inverters 224, 226 and two transistor devices 260, 262 that areimplemented as PMOS transistors. The inverter 224 includes an NMOStransistor 266 and a PMOS transistor 268 connected in series with eachother. Gate terminals, “G,” of the NMOS transistor 266 and the PMOStransistor 268 are connected to a source terminal or drain terminal ofthe NMOS transistor 258. The PMOS transistor 260 is connected to a highvoltage rail 270 with a positive voltage, “VDD,” and to the inverter224. The inverter 226 includes an NMOS transistor 276 and a PMOStransistor 278 connected in series with each other. Gate terminals, “G,”of the NMOS transistor 276 and the PMOS transistor 278 are connected toa source terminal or drain terminal of the NMOS transistor 256. The PMOStransistor 262 is connected to the high voltage rail 270 with thepositive voltage, “VDD,” and to the inverter 226. The transistors 266,276 are connected to a low voltage rail 280 that is connected to ground.In the embodiment depicted in FIG. 2, PMOS transistors 260, 268 arestacked together while PMOS transistors 262, 278 are stacked together.Stacked PMOS transistors in the slave inverter circuit helps to mitigateleakage current. In the embodiment depicted in FIG. 2, input data awarepower gating is implemented using floating power gating for the slaveinverter circuit. Specifically, the gate terminal, “G,” of the PMOStransistor 262 is connected to the node 282 that is connected to theNMOS transistor 256 and the gate terminal, “G,” of the PMOS transistor260 is connected to a node 272 that is connected to the NMOS transistor258. The latch circuit 200 enables relaxed transistor sizes because thefloating connection of the slave CCIP to the voltage rail 270 that isdependent on the input data of the latch circuit can facilitate andaccelerate the overpowering of the state of the slave CCIP 222. Comparedto other latch circuits, the latch circuit depicted in FIG. 2 does notrequire internal clock signal inversion. Absence of an internal clockinverter pair reduces unnecessary power consumption caused by theredundant clock transitions in which the input data remains the same forconsecutive clock cycles of the clock signal, “CK,” because all theinternal charging and discharging of the capacitances of the latchcircuit 200 occur when the input data of the latch circuit 200 changes.

Turning back to FIG. 1, in some embodiments, input data aware powergating is implemented for the slave inverter circuit 108 in which gateterminals of the two transistor devices 128, 130 are cross-connected tonodes between two switches of the switching unit 104 and the firstcross-coupled pair of inverters 112. FIG. 3 depicts an embodiment of thelatch circuit 100 depicted in FIG. 1 in which gate terminals of the twotransistor devices 260, 262 of a slave inverter circuit 308 arecross-connected to nodes between a switching unit 204 and across-coupled inverter pair (CCIP) 222 (referred to as the slave CCIP)of the slave inverter circuit 308. In the embodiment depicted in FIG. 3,a latch circuit 300 includes the input terminal, “DIN,” the switchingunit 204, a master inverter circuit 206 having a master CCIP 212, theslave inverter circuit 308 having the slave CCIP 222, the inverter 227,and the output terminal, “DOUT.” The difference between the latchcircuit 300 depicted in FIG. 3 and the latch circuit 200 depicted inFIG. 2 is the connections of the floating gate terminals, “G,” of thePMOS transistors 260, 262. In the embodiment depicted in FIG. 3, inputdata aware power gating is implemented using floating power gating forthe slave CCIP 222. Specifically, the gate terminal, “G,” of the PMOStransistor 260 is connected to a node 372 that is connected to the NMOStransistor 258 and the inverters 214, 216 of the master inverter circuitwhile the gate terminal, “G,” of the PMOS transistor 262 is connected toa node 382 that is connected to the NMOS transistor 256 and theinverters 214, 216 of the master inverter circuit. The latch circuit 300enables relaxed transistor sizes because of the floating connection ofthe slave CCIP to the voltage rail 270 dependent on the input data ofthe latch circuit can facilitate and accelerate the overpowering of thestate of the slave CCIP 222. Compared to other latch circuits, the latchcircuit depicted in FIG. 3 does not require an internal clock signalinversion, which reduces unnecessary power consumption caused by theredundant clock transitions.

Turning back to FIG. 1, in some embodiments, input data aware powergating is implemented for both the slave inverter circuit 108 and themaster inverter circuit 106. FIG. 4 depicts an embodiment of the latchcircuit 100 depicted in FIG. 1 in which input data aware power gating isimplemented for a slave inverter circuit 308 and the master invertercircuit 406. In the embodiment depicted in FIG. 4, the latch circuit 400includes the input terminal, “DIN,” the switching unit 204, the masterinverter circuit 406 having a master CCIP 412, the slave invertercircuit 308 having a slave CCIP 222, the inverter 227, and the outputterminal, “DOUT.” In the embodiment depicted in FIG. 4, the masterinverter circuit 406 includes the cross-coupled pair 412 of inverters414, 416 and two transistor devices 460, 462 that are implemented asPMOS transistors. The inverter 414 includes an NMOS transistor 466 and aPMOS transistor 468 connected in series with each other. Gate terminals,“G,” of the NMOS transistor 466 and the PMOS transistor 468 areconnected to a source terminal or drain terminal of the PMOS transistor252. The PMOS transistor 460 is connected to the high voltage rail 270with the positive voltage, “VDD,” and to the inverter 414. The inverter416 includes an NMOS transistor 476 and a PMOS transistor 478 connectedin series with each other. Gate terminals, “G,” of the NMOS transistor476 and the PMOS transistor 478 are connected to a source terminal ordrain terminal of the PMOS transistor 250. The PMOS transistor 462 isconnected to the high voltage rail 270 with the positive voltage, “VDD,”and to the inverter 416. The transistors 466, 476 are connected to a lowvoltage rail 280 that is connected to the ground. In the embodimentdepicted in FIG. 4, PMOS transistors 460, 468 are stacked together whilePMOS transistors 462, 478 are stacked together. Stacked PMOS transistorsin the slave inverter circuit and the master inverter circuit helps tomitigate the leakage current. In the embodiment depicted in FIG. 4,input data aware power gating is implemented using floating power gatingfor slave cross-coupled inverters and master cross-coupled inverters.Specifically, the gate terminal, “G,” of the PMOS transistor 460 isconnected to a node 472 at the output of the inverter 246 that isconnected to the PMOS transistor 252, while the gate terminal of thePMOS transistor 462 is connected to a node 482 at the output of theinverter 244 that is connected to the PMOS transistor 250. In the latchcircuit depicted in FIG. 4, the internal nodes (e.g., DBN, DB) of thelatch circuit are discharged or charged only when the input datareceived at the input terminal, “DIN,” is different for consecutiveclock cycles of the clock signal, “CK.” Compared to other latchcircuits, the latch circuit depicted in FIG. 4 does not require internalclock signal inversion. The absence of an internal clock inverter pairreduces unnecessary power consumption caused by redundant clocktransitions in which the input data remains the same for consecutiveclock cycles of the clock signal, “CK.”

Some examples of operation of the latch circuit 400 depicted in FIG. 4are described with respect to signal value transitions labeled in FIGS.5-7. Specifically, FIG. 5 shows the latch circuit of FIG. 4 with a lowphase of the clock signal, “CK.” In the embodiment depicted in FIG. 5,the input data at the input terminal, “DIN,” transitions from “1” to“0.” Because of the inverters 244, 246, signals at the PMOS transistors250, 252 are “1” and “0,” respectively. The transition of the input dataturns off the PMOS transistor 462, which is stacked to the inverter 416holding the logic value “1,” and facilitates overpowering of the masterCCIP data.

FIG. 6 shows the latch circuit 400 of FIG. 4 with a rising edge of theclock signal, “CK.” In the embodiment depicted in FIG. 6, the transitionof the input data turns off the PMOS transistor 262, which is stacked tothe inverter 226 holding “1,” and facilitates overpowering of the slaveCCIP data.

FIG. 7 shows the latch circuit 400 of FIG. 4 in an active hold state. Inthe embodiment depicted in FIG. 7, the output data at the outputterminal, “DOUT,” is at “0.” The stacked PMOS transistors in the masterCCIP and the slave CCIP limit the leakage current.

FIG. 8 shows the latch circuit 300 of FIG. 3 in a retention state. Inthe embodiment depicted in FIG. 8, the states of the slave CCIP 222 andthe master CCIP 212 are retained. In the retention state, the outputdata at the output terminal, “DOUT,” is at “0.” The clock signal, “CK,”is at logical high such that internal latch information from the inputterminal, “DIN,” is isolated as PMOS transistors 250, 252 are turnedOFF. The redundancy (duplication) of stored states in the master CCIPand the slave CCIP provides an extra resilience against data flips riskduring retention. The stacked OFF transistors (e.g., transistors 262,278 the slave inverter circuit 308) helps to mitigate the leakagecurrent. The latch circuit does not need extra control signals as usedin balloon latch type retention flip flop circuits.

FIG. 9 illustrates an example of signals of the latch circuits 300, 400depicted in FIG. 3 and FIG. 4. In the embodiment depicted in FIG. 9, theclock input, “CLK,” the data input at the terminal, “DIN,” the dataoutput at the terminal, “DOUT”, the input at node, “Q,” and the invertedinput at node, “QB,” to the slave CCIP, and the input at node, “GP,” andinverted input at node, “GN,” to the master CCIP are shown. The internalnodes of the latch circuits, (e.g., GP, GN, QB, Q) are discharged orcharged only when the input data received at the input terminal, “DIN,”is different for consecutive clock cycles of the clock signal, “CK.”

FIG. 10 is a process flow diagram that illustrates a method foroperating a latch circuit in accordance with another embodiment of theinvention. The latch circuit may be, for example, the same as or similarto the latch circuit 100 depicted in FIG. 1, the latch circuit 200depicted in FIG. 2, the latch circuit 300 depicted in FIG. 3, and/or thelatch circuit 400 depicted in FIG. 4. At block 1002, input data isreceived at the latch circuit. At block 1004, input nodes of across-coupled pair of inverters of the latch circuit are discharged orcharged if the input data is different for consecutive clock cycles ofthe latch circuit.

Although the operations of the method herein are shown and described ina particular order, the order of the operations of the method may bealtered so that certain operations may be performed in an inverse orderor so that certain operations may be performed, at least in part,concurrently with other operations. In another embodiment, instructionsor sub-operations of distinct operations may be implemented in anintermittent and/or alternating manner.

In addition, although specific embodiments of the invention that havebeen described or depicted include several components described ordepicted herein, other embodiments of the invention may include fewer ormore components to implement less or more features.

Furthermore, although specific embodiments of the invention have beendescribed and depicted, the invention is not to be limited to thespecific forms or arrangements of parts so described and depicted. Thescope of the invention is to be defined by the claims appended heretoand their equivalents.

What is claimed is:
 1. A latch circuit, comprising: an input terminalconfigured to receive an input data signal; a switching unit configuredto control application of the input data signal; a first invertercircuit connected to the switching unit, wherein the first invertercircuit comprises a first cross-coupled pair of inverters; and a secondinverter circuit connected to the first inverter circuit through theswitching unit, wherein the second inverter circuit comprises: a secondcross-coupled pair of inverters; and two transistor devices, whereineach inverter of the second cross-coupled pair of inverters is connectedto a voltage rail through a corresponding transistor device, and whereineach of the two transistor devices is connected to a node that isbetween the switching unit and the first inverter circuit or the secondinverter circuit.
 2. The latch circuit of claim 1, wherein gateterminals of the two transistor devices are cross-connected to nodesbetween two switches of the switching unit and the second cross-coupledpair of inverters.
 3. The latch circuit of claim 1, wherein gateterminals of the two transistor devices are cross-connected to nodesbetween two switches of the switching unit and the first cross-coupledpair of inverters.
 4. The latch circuit of claim 1, wherein the twotransistor devices comprise two PMOS transistors.
 5. The latch circuitof claim 1, wherein the first inverter circuit further comprises: twotransistor devices, wherein each inverter of the first cross-coupledpair of inverters is connected to the voltage rail through acorresponding transistor device, and wherein gate terminals of the twotransistor devices of the first inverter circuit are cross-connected tonodes within the switching unit.
 6. The latch circuit of claim 5,wherein the two transistor devices of the first inverter circuitcomprise two PMOS transistors.
 7. The latch circuit of claim 1, whereineach of the two transistor devices comprises a PMOS transistor connectedto a high voltage rail and to a corresponding inverter of the secondcross-coupled pair of inverters.
 8. The latch circuit of claim 1,wherein each inverter of the second inverter circuit comprises an NMOStransistor and a PMOS transistor connected in series with each other,and where gate terminals of the NMOS transistor and the PMOS transistorare connected to the switching unit.
 9. The latch circuit of claim 1,wherein the switching unit is configured to control the application ofthe input data signal to the first cross-coupled pair of inverters andto the second cross-coupled pair of inverters.
 10. The latch circuit ofclaim 1, wherein the switching unit comprises: a third inverter circuitconfigured to generate an inverted version of the input data signal anda non-inverted version of the input data signal; and a switching moduleconfigured to switch one of the inverted and non-inverted versions ofthe input data signal to an input terminal of the first cross-coupledpair of inverters or the second cross-coupled pair of inverters and toswitch the other one of the inverted and non-inverted versions of theinput data signal to an output terminal of the first cross-coupled pairof inverters or the second cross-coupled pair of inverters.
 11. Thelatch circuit of claim 10, wherein the third inverter circuit comprises:a first inverter connected to the input terminal and configured togenerate the inverted version of the input data signal; and a secondinverter configured to generate the non-inverted version of the inputdata signal.
 12. The latch circuit of claim 10, wherein the switchingmodule comprises: a first set of switches configured to switch one ofthe inverted and non-inverted versions of the input data signal to aninput terminal of the first cross-coupled pair of inverters and toswitch the other one of the inverted and non-inverted versions of theinput data signal to an output terminal of the first cross-coupled pairof inverters; and a second set of switches configured to switch one ofthe inverted and non-inverted versions of the input data signal to aninput terminal of the second cross-coupled pair of inverters and toswitch the other one of the inverted and non-inverted versions of theinput data signal to an output terminal of the second cross-coupled pairof inverters.
 13. The latch circuit of claim 12, wherein the first setof switches comprises transistors of a first polarity type, and thesecond set of switches comprises transistors of a second, opposite,polarity type.
 14. The latch circuit of claim 12, wherein the first setof switches comprises PMOS transistors, and the second set of switchescomprises NMOS transistors.
 15. The latch circuit of claim 12, furthercomprising an output terminal connected to the switching unit and thesecond inverter circuit and configured to output an output data signalin response to the input data signal.
 16. A latch circuit, comprising:an input terminal configured to receive an input data signal; aswitching unit comprising: a first inverter configured to generate aninverted version of the input data signal from the input data signal; asecond inverter connected to the first inverter and configured togenerate a non-inverted version of the input data signal; a first set ofswitching transistors of a first polarity type, wherein the first set ofswitching transistors are connected to the first and second inverters;and a second set of switching transistors of a second, opposite,polarity type; a first inverter circuit connected to the first andsecond sets of switching transistors, wherein the first inverter circuitcomprises a first cross-coupled pair of inverters; and a second invertercircuit connected to the first inverter circuit through the second setof switching transistors, wherein the second inverter circuit comprises:a second cross-coupled pair of inverters; and two transistor devices,wherein each inverter of the second cross-coupled pair of inverters isconnected to a low voltage rail and to a high voltage rail through acorresponding transistor device, wherein gate terminals of the twotransistor devices are cross-connected to drain terminals or sourceterminals of the second set of switching transistors.
 17. The latchcircuit of claim 16, wherein the gate terminals of the two transistordevices are cross-connected to the second cross-coupled pair ofinverters.
 18. The latch circuit of claim 16, wherein the gate terminalsof the two transistor devices are cross-connected to the firstcross-coupled pair of inverters.
 19. The latch circuit of claim 16,wherein the first inverter circuit further comprises: two transistordevices for connecting the first cross-coupled pair of inverters to thehigh voltage rail.
 20. A method for operating a latch circuit, themethod comprising: receiving input data at the latch circuit; anddischarging or charging input nodes of a cross-coupled pair of invertersof the latch circuit if the input data is different for consecutiveclock cycles of the latch circuit.